1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device, particularly to an electrically erasable programmable ROM (EEPROM).
2. Description of the Related Art
In an EEPROM having memory cells each formed of a single transistor, the transistor has a double gate structure having a floating gate and a control gate.
In such a transistor having the double gate structure, writing of information is performed by accelerating hot electrons generated on a drain side of the floating gate toward a source side thereof, and injecting the hot electrons in the floating gate through the gate insulation film.
Reading of information is performed by detecting a difference between operating characteristics of memory cell transistors by judging whether or not a charge is injected into each of the floating gates.
There are two types of structures of such memory cells. One is a stacked gate type, and another is a split gate type. In memory cells of split gate type, as shown in FIG. 6, a floating gate 4 is formed above a channel formed between a drain 1 and a source 2 with an insulation film 3 interposed between the floating gate 4 itself and the channel and, partially overlapping the source 2. Furthermore, a control gate 5 is formed, partially overlapping the floating gate 4 with the insulation film 6 interposed therebetween.
A structure of a non-volatile semiconductor memory device using such memory cells of split gate type is briefly shown in FIG. 7. The memory cell array is formed of a plurality of memory cells disposed in a matrix of n rows and m columns.
Each of the memory cells is disposed in each of intersections between n number of word lines WL0 to Wn−1 and m number of bit lines BL0 to BLm−1. A control gate (indicated by numeral 5 in FIG. 6) of the memory cell in each of the rows is connected with one of the word lines WL0 to Wn−1, and a drain (indicated by numeral 1 in FIG. 6) thereof is connected with one of the bit lines BL0 to BLm−1.
A source (indicated by numeral 2 in FIG. 6) of the memory cell in each of the rows is connected with a common source line SL. Note that FIG. 7 shows only m pieces of memory cells M0 to Mm−1 connected with a word line WLk in a k-th row in the above-described memory cell array.
A row address decoder 10 supplies a voltage corresponding to a program mode, a read mode and an erase mode, to the common source line SL relating to a selected word line (e.g. word line WLk). A column address decoder 11 selects one (e.g. bit line BLj) of m number of the bit lines BL0 to BLm−1 in the program mode and the read mode.
A voltage controlled by a write circuit 12 is applied to the selected bit line BLj in the program mode, and the selected bit line BLj is connected to a sense amplifier 13 in the read mode.
Next, the erase, program and read operations of the above-described non-volatile semiconductor memory device will be described.
(1) Erase Operation
The column address decoder 11 applies ground potential (0V) to all the bit lines BL0 to BLm−1, and the row address decoder 10 applies an erase voltage (14.5 V) to all the word lines WL0 to Wn−1. Then, the erase voltage (e.g. 14.5 V) is applied to the control gates 5 of all the memory cells, and a voltage of 0V is applied to the drains 1 and the sources 2.
With respect to the memory cells M0 to Mm−1 connected with the word line WLk, capacitive coupling between the sources 2 and the floating gates 4 is larger than capacitive coupling between the control gates 5 and the floating gates 4 so that electric potential of the floating gates 4 is fixed at 0V, which is the same voltage as that of the sources 2, by the capacitive coupling with the sources 2. Then, a difference between electric potentials of the control gates 5 and the floating gates 4 becomes 14.5V so that a Fowler-Nordheim (F-N) tunnel current flows through a tunnel oxide film 6.
That is, electrons injected in the floating gates 4 are extracted from protruding portions of the floating gates 4 into the control gates 5. Batch erase of the memory cells M0 to Mm−1 connected with the word line WLk is thus performed.
(2) Program Operation (Write Operation)
The row address decoder 10 selects the word line WLk, for example, based on applied row address data RAD. Then, the row address decoder 10 applies a select voltage Vgp (e.g. 2.0V) to this word line WLk, and a ground voltage 0V to other non-selected word lines. Furthermore, the row address decoder 10 supplies a program voltage Vp (e.g. 12.2V) to the common source line SL corresponding to the selected word line WLk.
The column address decoder 11 connects the bit line BL (e.g. BLj) selected based on column address data CAD to the write circuit 12. Therefore, the selected bit line BLj is applied with a voltage based on the write data applied to an input and output terminal I/O line 14.
For example, when the input and output I/O line 14 is applied with data “0”, the bit line BLj is applied with a write enable voltage Vse (e.g. 0.9V). When the input and output I/O line 14 is applied with data “1”, the bit line BLj is applied with a write disable voltage Vsd (e.g. 4.0V). The other non-selected bit lines are applied with a write disable voltage Vsd (e.g. 4.0V).
Therefore, at a memory cell Mj specified by the word line WLk and the bit line BLj, when the input and output I/O line 14 is applied with data “0”, the source 2 is applied with a voltage of 12.2V, the drain 1 is applied with a voltage of 0.9V, and the control gate 5 is applied with a voltage of 2.0V. This makes carrier flow from the drain 1 to the source 2. Here, the voltage of the floating gate 4 becomes approximately the same as that of the source 2 by capacitive coupling between the floating gate 4 and the source 2. Therefore, the carrier is injected into the floating gate 4 through the insulating film 3 as hot electrons.
On the other hand, when the input and output I/O line 14 is applied with data “1”, the source 2 of the memory cell Mj is applied with a voltage of 12.2V, the drain 1 thereof is applied with a voltage of 4.0V, and the control gate 5 thereof is applied with a voltage of 2.0V. Therefore, the memory cell Mj turns off so that the carrier does not flow into the floating gate 4.
Furthermore, in the non-selected memory cells, too, the voltages applied to the drain 1, the source 2, and the control gate 5 do not satisfy program conditions so that the carrier is not injected to the floating gate 4.
(3) Read Operation
The row address decoder 10 applies a select voltage Vgr (e.g. 4.0V) to the word line WL (e.g. word line WLk) selected based on the row address data RAD, and applies a ground voltage (0V) to all the common source line SL. On the other hand, the column address decoder 11 connects the bit line BL (e.g. bit line BLj) selected based on the column address data CAD to the sense amplifier 13.
Reading of data stored in the memory cell Mj specified by the word line WLk and the bit line BLj is performed. At this time, the sense amplifier 13 performs judgment of the read data based on quantitative relation between a reference current Iref of a predetermined amount and a cell current Ir flowing in the memory cell Mj. That is, the sense amplifier 13 judges the data to be “1” when the cell current Ir is larger than the reference current Iref, or judges the data to be “0” when the cell current Ir is smaller than the reference current Iref.
However, the cell current Ir in the read mode varies by various factors such as time passing or disturbance during programming. For example, when data in a certain memory cell Mj is “1” (i.e., in a state where the floating gate 4 is not injected with carrier), the carrier enters the floating gate 4 from a substrate with time so that the cell current Ir reduces.
The reference current Iref is a constant current. Therefore, when the cell current Ir becomes lower than the reference current Iref, the data “1” changes into the data “0”. Thus, data retention characteristics deteriorates.
Furthermore, the above-described non-volatile semiconductor memory device has a problem that it requires a long time to rewrite the data. For example, when data “1” programmed in a certain memory cell Mj is to be changed into data “0”, the above-described program operation is performed. This operation can be performed with relatively short time (several μ sec) since a method of injecting hot electrons into the floating gate 4 through the insulation film 3 is employed. On the other hand, when data “0” programmed in a certain memory cell Mj is to be changed into data “1,” the erase operation is performed. However, this operation takes as long as several m sec by employing a conventional method of extracting electrons injected in the floating gate 4 into the control gate 5 by flowing a F-N tunnel current.